Low-voltage CMOS circuits for analog decoders

This paper presents a novel circuit architecture for implementing analog Turbo-style decoders in subthreshold CMOS with low supply voltage. Various analog Turbo decoding circuits have been demonstrated in recent years which require significantly less power and silicon area than digital circuits while providing high throughput. As CMOS process technologies improve, allowable supply voltages are reduced. We present circuits which can operate at lower supply voltages than other published analog architectures. Our low-voltage circuits also escape the need for regulated bias voltages, which are required by other CMOS analog architectures. In addition, low-voltage analog decoders can be implemented in the most advanced CMOS processes which cannot sustain supply voltages greater than 1.2V. Other CMOS analog decoders have been shown to operate with supplies as low as 1.2V. Our circuits have been simulated with supplies as low as .4V.